The present invention relates to testing of wireless devices, and in particular, to controlling timing of transmissions by a data packet signal transceiver device under test (DUT) by transmitting congestive communication channel signals to cause the DUT to detect apparent communication channel activity and delay its own signal transmissions.
Many of today's electronic devices use wireless signal technologies for both connectivity and communications purposes. Because wireless devices transmit and receive electromagnetic energy, and because two or more wireless devices have the potential of interfering with the operations of one another by virtue of their signal frequencies and power spectral densities, these devices and their wireless signal technologies must adhere to various wireless signal technology standard specifications.
When designing such wireless devices, engineers take extra care to ensure that such devices will meet or exceed each of their included wireless signal technology prescribed standard-based specifications. Furthermore, when these devices are later being manufactured in quantity, they are tested to ensure that manufacturing defects will not cause improper operation, including their adherence to the included wireless signal technology standard-based specifications.
Testing of such wireless devices typically involves testing of the receiving and transmitting subsystems of the device under test (DUT). The testing system will send a prescribed sequence of test data packet signals to a DUT, e.g., using different frequencies, power levels, and/or signal modulation techniques to determine if the DUT receiving subsystem is operating properly. Similarly, the DUT will send test data packet signals at a variety of frequencies, power levels, and/or modulation techniques for reception and processing by the testing system to determine if the DUT transmitting subsystem is operating properly.
For testing these devices following their manufacture and assembly, current wireless device test systems typically employ testing systems having various subsystems for providing test signals to each device under test (DUT) and analyzing signals received from each DUT. Some systems (often referred to as “testers”) include, at least, one or more sources of test signals (e.g., in the form of a vector signal generator, or “VSG”) for providing the source signals to be transmitted to the DUT, and one or more receivers (e.g., in the form of a vector signal analyzer, or “VSA”) for analyzing signals produced by the DUT. The production of test signals by the VSG and signal analysis performed by the VSA are generally programmable (e.g., through use of an internal programmable controller or an external programmable controller such as a personal computer) so as to allow each to be used for testing a variety of devices for adherence to a variety of wireless signal technology standards with differing frequency ranges, bandwidths and signal modulation characteristics.
Referring to FIG. 1, a typical testing environment 10a includes a tester 12 and a DUT 16, with test data packet signals 21t and DUT data packet signals 21d exchanged as RF signals conveyed between the tester 12 and DUT 16 via a conductive signal path 20a, typically in the form of co-axial RF cable 20c and RF signal connectors 20tc, 20dc. As noted above, the tester typically includes a signal source 14g (e.g., a VSG) and a signal analyzer 14a (e.g., a VSA). The tester 12 and DUT 16 may also include preloaded information regarding predetermined test sequences, typically embodied in firmware 14f within the tester 12 and firmware 18f within the DUT 16. The testing details within this firmware 14f, 18f about the predetermined test flows typically require some form of explicit synchronization between the tester 12 and DUT 16, typically via the data packet signals 21t, 21d. Alternatively, testing may be controlled by a controller 30 which may be integral to the tester 12 or external (e.g., a programmed personal computer) as depicted here. The controller 30 may communicate with the DUT 16 via one or more signal paths (e.g., Ethernet cabling, etc.) 31d to convey commands and data. If external to the tester 12, the controller 30 may further communicate with the tester 12 via one or more additional signal paths (e.g., Ethernet cabling, etc.) 31t to convey additional commands and data.
Referring to FIG. 2, an alternative testing environment 10b uses a wireless signal path 20b via which the test data packet signals 21t and DUT data packet signals 21d may be communicated via respective antenna systems 20ta, 20da of the tester 12 and DUT 16.
Ordinarily when testing a wireless device (e.g., wireless fidelity (WiFi), Bluetooth, Zigbee, Z-Wave or similar device) with a tester, once communications between tester and DUT have been established, the tester and DUT will execute a test flow during which the tester or controller controls the behavior of the DUT (e.g., by executing control commands via driver software associated with the DUT). Commands may include instructing the DUT to receive test packets from the tester, or to transmit packets to the tester. The characteristics of the packets may also be controlled, such as power level, frequency, data rate, modulation, etc.
However, for some types of DUTs, such as Internet-of-Things (“IoT”) sensors or wearable devices, direct external control of the DUT may not be practical or possible. In such cases, testing must typically be performed by the tester interacting directly with the DUT, e.g., with strict synchronization between the tester and DUT via only a wired 20a or wireless 20b signal path for the communication channel with no dedicated signal paths 31b for control signals. However, as these DUTs are usually based on real application stacks, they follow specific timing manners and are impossible to wait for the tester.
Referring to FIG. 3, for example, following an initial communication from the tester, the DUT may respond during a subsequent time interval 42 with a packet 21da (e.g., an acknowledgement, or “ACK”) for capture and processing (e.g., storage, analysis, etc.) by the tester. Meanwhile, as the tester begins operating in a pre- or post-processing mode 44 with the received packet 21da, the DUT may continue (e.g., with a sequence of asynchronous operations independent of other external stimuli, or with a sequence of synchronous operations in response to the initial tester communication) by transmitting further packets 21db, 21dc, which may be missed by the tester, e.g., during the processing interval 44 or later due to a subsequent tester capture and response time interval 46 starting after transmission of a DUT packet 21dc has been initiated. Such missed DUT packets 21db, 21dc could result in the tester failing to catch up and/or keep pace with the DUT, in terms of capturing further DUT packets, as well as the DUT assuming that its communication link with the tester has failed or been otherwise lost, and thereby likely result in a failed test or at least an incomplete test.
Therefore, for a robust test of the DUT under its expected operating conditions, the processing capabilities of the tester would need to be sufficiently high to ensure completion in time to capture all subsequent DUT packets. Such a level of tester performance, in terms of processing speeds, is significantly higher than what is normally sufficient (e.g., as when the tester is allowed to control the rate of test operations) and results in significantly increased test equipment costs.